NXP Semiconductors /MIMXRT1021 /BEE /CTRL

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Interpret as CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BEE_ENABLE_0)BEE_ENABLE 0 (CTRL_CLK_EN)CTRL_CLK_EN 0 (CTRL_SFTRST_N)CTRL_SFTRST_N 0 (KEY_VALID)KEY_VALID 0 (KEY_REGION_SEL_0)KEY_REGION_SEL 0 (AC_PROT_EN)AC_PROT_EN 0 (LITTLE_ENDIAN_0)LITTLE_ENDIAN 0SECURITY_LEVEL_R0 0 (CTRL_AES_MODE_R0_0)CTRL_AES_MODE_R0 0SECURITY_LEVEL_R1 0 (CTRL_AES_MODE_R1_0)CTRL_AES_MODE_R1 0 (BEE_ENABLE_LOCK)BEE_ENABLE_LOCK 0 (CTRL_CLK_EN_LOCK)CTRL_CLK_EN_LOCK 0 (CTRL_SFTRST_N_LOCK)CTRL_SFTRST_N_LOCK 0 (REGION1_ADDR_LOCK)REGION1_ADDR_LOCK 0 (KEY_VALID_LOCK)KEY_VALID_LOCK 0 (KEY_REGION_SEL_LOCK)KEY_REGION_SEL_LOCK 0 (AC_PROT_EN_LOCK)AC_PROT_EN_LOCK 0 (LITTLE_ENDIAN_LOCK)LITTLE_ENDIAN_LOCK 0SECURITY_LEVEL_R0_LOCK 0 (CTRL_AES_MODE_R0_LOCK)CTRL_AES_MODE_R0_LOCK 0 (REGION0_KEY_LOCK)REGION0_KEY_LOCK 0SECURITY_LEVEL_R1_LOCK 0 (CTRL_AES_MODE_R1_LOCK)CTRL_AES_MODE_R1_LOCK 0 (REGION1_KEY_LOCK)REGION1_KEY_LOCK

BEE_ENABLE=BEE_ENABLE_0, CTRL_AES_MODE_R1=CTRL_AES_MODE_R1_0, CTRL_AES_MODE_R0=CTRL_AES_MODE_R0_0, KEY_REGION_SEL=KEY_REGION_SEL_0, LITTLE_ENDIAN=LITTLE_ENDIAN_0

Description

Control Register

Fields

BEE_ENABLE

BEE enable bit

0 (BEE_ENABLE_0): Disable BEE

1 (BEE_ENABLE_1): Enable BEE

CTRL_CLK_EN

Clock enable input, low inactive

CTRL_SFTRST_N

Soft reset input, low active

KEY_VALID

AES-128 key is ready Load AES key by changing this bit from 0 to 1.

KEY_REGION_SEL

AES key region select

0 (KEY_REGION_SEL_0): Load AES key for region0

1 (KEY_REGION_SEL_1): Load AES key for region1

AC_PROT_EN

Enable access permission control When AC_PROT_EN is asserted, all encrypted regions are limited to be ARM core access only

LITTLE_ENDIAN

Endian swap control for the 16 bytes input and output data of AES core.

0 (LITTLE_ENDIAN_0): The input and output data of the AES core is swapped as below: {B15,B14,B13,B12,B11,B10,B9,B8, B7,B6,B5,B4,B3,B2,B1,B0} swap to {B0,B1,B2,B3,B4,B5,B6,B7, B8,B9,B10,B11,B12,B13,B14,B15}, where B0~B15 refers to Byte0 to Byte15.

1 (LITTLE_ENDIAN_1): The input and output data of AES core is not swapped.

SECURITY_LEVEL_R0

Security level of the allowed access for memory region0

CTRL_AES_MODE_R0

AES mode of region0

0 (CTRL_AES_MODE_R0_0): ECB

1 (CTRL_AES_MODE_R0_1): CTR

SECURITY_LEVEL_R1

Security level of the allowed access for memory region1

CTRL_AES_MODE_R1

AES mode of region1

0 (CTRL_AES_MODE_R1_0): ECB

1 (CTRL_AES_MODE_R1_1): CTR

BEE_ENABLE_LOCK

Lock bit for bee_enable

CTRL_CLK_EN_LOCK

Lock bit for ctrl_clk_en

CTRL_SFTRST_N_LOCK

Lock bit for ctrl_sftrst

REGION1_ADDR_LOCK

Lock bit for region1 address boundary

KEY_VALID_LOCK

Lock bit for key_valid

KEY_REGION_SEL_LOCK

Lock bit for key_region_sel

AC_PROT_EN_LOCK

Lock bit for ac_prot

LITTLE_ENDIAN_LOCK

Lock bit for little_endian

SECURITY_LEVEL_R0_LOCK

Lock bits for security_level_r0

CTRL_AES_MODE_R0_LOCK

Lock bit for region0 ctrl_aes_mode

REGION0_KEY_LOCK

Lock bit for region0 AES key

SECURITY_LEVEL_R1_LOCK

Lock bits for security_level_r1

CTRL_AES_MODE_R1_LOCK

Lock bit for region1 ctrl_aes_mode

REGION1_KEY_LOCK

Lock bit for region1 AES key

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